SN74LVTH244ADWR 供应商
-
SN74LVTH244ADWR
品牌:TI 封装/批号:原厂原装/22+ -
SN74LVTH244ADWR
品牌:TI/德州仪器 封装/批号:SOP/21+ -
SN74LVTH244ADWR
品牌:TI 封装/批号:/ -
SN74LVTH244ADWR
品牌:TI(德州仪器) 封装/批号:SOIC-20_300mil/2022+ -
SN74LVTH244ADWR
品牌:TI代理 封装/批号:SOP-20/23+ -
SN74LVTH244ADWR
品牌:TI 封装/批号:/21+ -
SN74LVTH244ADWR
品牌:TI 封装/批号:SOP--7.2/22+ -
SN74LVTH244ADWR
品牌:TI 封装/批号:SOP-20/23+
SN74LVTH244ADWR 属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74LVTH
- 逻辑类型:缓冲器/线路驱动器,非反相
- 元件数:2
- 每个元件的位元数:4
- 输出电流高,低:32mA,64mA
- 电源电压:2.7 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:20-SOIC(0.295",7.50mm 宽)
- 供应商设备封装:20-SOIC
- 包装:®
- 其它名称:296-1270-6
产品特性
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Support Unregulated Battery Operation Down to 2.7 V
- Ioff and Power-Up 3-State Support Hot Insertion
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.The LVTH244A devices are organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the devices pass data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.