SN74LVC2952APWR 供应商
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SN74LVC2952APWR
品牌：TI 封装/批号：原厂原装/22+
SN74LVC2952APWR 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 缓冲器，驱动器，接收器，收发器
- 系列：74LVC
- 逻辑类型：收发器，非反相
- 元件数：1
- 每个元件的位元数：8
- 输出电流高，低：24mA，24mA
- 电源电压：1.65 V ~ 3.6 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：24-TSSOP（0.173"，4.40mm 宽）
- 供应商设备封装：24-TSSOP
- 包装：®
- 其它名称：296-8508-6
产品特性
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 8.2 ns at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
产品概述
This octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.The SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA)\ input is low. Taking the output-enable (OEAB\ or OEBA)\ input low accesses the data on either port.Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
SN74LVC2952APWR