SN74LVC125AIPWREP 供应商
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SN74LVC125AIPWREP
品牌：TI 封装/批号：原厂原装/22+ -
SN74LVC125AIPWREP
品牌：TI(德州仪器) 封装/批号：TSSOP-14/2022+
SN74LVC125AIPWREP 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 缓冲器，驱动器，接收器，收发器
- 系列：74LVC
- 逻辑类型：缓冲器/线路驱动器，非反相
- 元件数：4
- 每个元件的位元数：1
- 输出电流高，低：24mA，24mA
- 电源电压：1.65 V ~ 3.6 V
- 工作温度：-40°C ~ 125°C
- 安装类型：表面贴装
- 封装/外壳：14-TSSOP（0.173"，4.40mm 宽）
- 供应商设备封装：14-TSSOP
- 包装：®
- 其它名称：296-22333-6
产品特性
- Controlled BaselineOne Assembly/Test Site, One Fabrication Site
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.8 ns at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.