SN74LV245ATPWR 供应商
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SN74LV245ATPWR
品牌：TI 封装/批号：原厂原装/22+ -
SN74LV245ATPWR
品牌：TI 封装/批号：/05+ -
SN74LV245ATPWR
品牌：SN74LV245ATPWR 封装/批号：TI/连可连代销V -
SN74LV245ATPWR
品牌：TI 封装/批号：TSSOP/23+
SN74LV245ATPWR 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 缓冲器，驱动器，接收器，收发器
- 系列：74LV
- 逻辑类型：收发器，非反相
- 元件数：1
- 每个元件的位元数：8
- 输出电流高，低：16mA，16mA
- 电源电压：2 V ~ 5.5 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：20-TSSOP（0.173"，4.40mm 宽）
- 供应商设备封装：20-TSSOP
- 包装：®
- 其它名称：296-17771-6
产品特性
- Inputs Are TTL-Voltage Compatible
- 4.5-V to 5.5-V VCC Operation
- Typical tpd of 3.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C
- Supports Mixed-Mode Voltage Operation on All Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
产品概述
This octal bus transceiver is designed for asynchronous two-way communication between
data buses. The control-function implementation minimizes external timing requirements.The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to
the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable
(OE) input can be used to disable the device so that the buses are
effectively isolated.To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the
driver.This device is fully specified for partial-power-down applications using
Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.