SN74ALVCH16952DGGR 供应商
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SN74ALVCH16952DGGR
品牌：TI 封装/批号：原厂原装/22+ -
SN74ALVCH16952DGGR
品牌：TI(德州仪器) 封装/批号：TSSOP-56/2022+
SN74ALVCH16952DGGR 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 缓冲器，驱动器，接收器，收发器
- 系列：74ALVCH
- 逻辑类型：寄存收发器，非反相
- 元件数：2
- 每个元件的位元数：8
- 输出电流高，低：24mA，24mA
- 电源电压：1.65 V ~ 3.6 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：56-TFSOP（0.240"，6.10mm 宽）
- 供应商设备封装：56-TSSOP
- 包装：®
- 其它名称：296-9780-6
产品特性
- Member of the Texas Instruments Widebus™ Family
- EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages
产品概述
This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCC operation.The SN74ALVCH16952 contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH16952 is characterized for operation from -40°C to 85°C.
SN74ALVCH16952DGGR