SN74ALVCH16825DGGR 供应商
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SN74ALVCH16825DGGR
品牌:TI 封装/批号:原厂原装/22+ -
SN74ALVCH16825DGGR
品牌:TI/德州仪器 封装/批号:21+/TSSOP56 -
SN74ALVCH16825DGGR
品牌:TI(德州仪器) 封装/批号:TSSOP-56/2022+
SN74ALVCH16825DGGR 属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74ALVCH
- 逻辑类型:缓冲器/线路驱动器,非反相
- 元件数:2
- 每个元件的位元数:9
- 输出电流高,低:24mA,24mA
- 电源电压:1.65 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:56-TFSOP(0.240",6.10mm 宽)
- 供应商设备封装:56-TSSOP
- 包装:®
- 其它名称:296-5252-6
产品特性
- Member of the Texas Instruments Widebus Family
- EPIC (Enhanced-Performance Implanted CMOS) Submicron Process
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
产品概述
This 18-bit buffer and line driver is designed for 1.65-V to 3.6-V VCC operation.This SN74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.The device can be used as two 9-bit buffers or one 18-bit buffer. It provides true data.The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.The SN74ALVCH16825 is characterized for operation from &$150;40°C to 85°C.