SN74ALVCH16543DLR 供应商
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SN74ALVCH16543DLR
品牌:TI 封装/批号:原厂原装/22+ -
SN74ALVCH16543DLR
品牌:TI(德州仪器) 封装/批号:SSOP-56/2022+
SN74ALVCH16543DLR 属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 缓冲器,驱动器,接收器,收发器
- 系列:74ALVCH
- 逻辑类型:寄存收发器,非反相
- 元件数:2
- 每个元件的位元数:8
- 输出电流高,低:24mA,24mA
- 电源电压:1.65 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:56-BSSOP(0.295",7.50mm 宽)
- 供应商设备封装:56-SSOP
- 包装:®
- 其它名称:296-14785-6
产品特性
- Member of the Texas Instruments Widebus Family
- EPIC (Enhanced-Performance Implanted CMOS) Submicron Process
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
产品概述
This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCC operation.The SN74ALVCH16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.The A-to-B enable (CEAB)\ input must be low to enter data from A or to output data from B. If CEAB is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using CEBA\, LEBA\, and OEBA\.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH16543 is characterized for operation from 40°C to 85°C.