SN74ABT125DBR 供应商
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SN74ABT125DBR
品牌：TI 封装/批号：原厂原装/22+ -
SN74ABT125DBR
品牌：TI 封装/批号：14SSOP/2019+ -
SN74ABT125DBR
品牌：TI 封装/批号：SSOP/03+ -
SN74ABT125DBR
品牌： 封装/批号：/23+ -
SN74ABT125DBR
品牌：TI 封装/批号：/2021+
SN74ABT125DBR 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 缓冲器，驱动器，接收器，收发器
- 系列：74ABT
- 逻辑类型：缓冲器/线路驱动器，非反相
- 元件数：4
- 每个元件的位元数：1
- 输出电流高，低：32mA，64mA
- 电源电压：4.5 V ~ 5.5 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：14-SSOP（0.209"，5.30mm 宽）
- 供应商设备封装：14-SSOP
- 包装：®
- 其它名称：296-3875-6
产品特性
- Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C
- High-Drive Outputs (–32-mA IOH, 64-mA IOL)
- Ioff and Power-Up 3-State Support Hot Insertion
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74ABT125DBR