74ACT11286D 供应商
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74ACT11286D
品牌：TI 封装/批号：原厂原装/22+ -
74ACT11286D
品牌：TI(德州仪器) 封装/批号：SOIC-14/2022+
74ACT11286D 属性参数
- 标准包装：50
- 类别：集成电路 (IC)
- 家庭：逻辑 - 奇偶校验发生器和校验器
- 系列：74ACT
- 逻辑类型：奇偶校验发生器/校验器
- 电路数：9 位
- 输出电流高，低：24mA，24mA
- 电源电压：4.5 V ~ 5.5 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：14-SOIC（0.154"，3.90mm 宽）
- 供应商设备封装：14-SOIC
- 其它名称：296-4196-5
产品特性
- Inputs Are TTL-Voltage Compatible
- Generates Either Odd or Even Parity for Nine Data Lines
- Cascadable for n-Bits Parity
- Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)
产品概述
The 74ACT11286 universal 9-bit parity generator/checker features a
local output for parity checking and a bus-driving parity I/O port
for parity generation/checking. The word-length capability is easily
expanded by cascading.The control input
is implemented specifically to accommodate cascading. When the is low, the parity tree is
disabled and the PARITY ERROR output remains at a high logic level,
regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR
indicates a parity error when either an even number of inputs (A
through I) are high and PARITY I/O is forced to a low logic level, or
when an odd number of inputs are high and PARITY I/O is forced to a
high logic level.The I/O control circuitry is designed so that the I/O port remains
in the high-impedance state during power up or power down, to prevent
bus glitches.The 74ACT11286 is characterized for operation from -40°C to
85°C.
74ACT11286D