SN74LVTH16374DL 供应商
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SN74LVTH16374DL
品牌:TI 封装/批号:原厂原装/22+ -
SN74LVTH16374DL
品牌:TI 封装/批号:TSSOP/23+ -
SN74LVTH16374DL
品牌:TI 封装/批号:PSOP/N/A -
SN74LVTH16374DL
品牌:TI代理 封装/批号:SSOP48/23+ -
SN74LVTH16374DLR
品牌: 封装/批号:48-SS/22+ -
SN74LVTH16374DLR
品牌:TI 封装/批号:/2019+ -
SN74LVTH16374DLR
品牌:TI(德州仪器) 封装/批号:SSOP-48/2022+ -
SN74LVTH16374DLR
品牌:TI 封装/批号:/2021+
SN74LVTH16374DL 属性参数
- 标准包装:25
- 类别:集成电路 (IC)
- 家庭:逻辑 - 触发器
- 系列:74LVTH
- 功能:标准
- 类型:D 型总线
- 输出类型:三态非反相
- 元件数:2
- 每个元件的位元数:8
- 频率 - 时钟:160MHz
- 延迟时间 - 传输:3ns
- 触发器类型:正边沿
- 输出电流高,低:32mA,64mA
- 电源电压:2.7 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:48-BSSOP(0.295",7.50mm 宽)
- 包装:管件
- 其它名称:296-1264-5
产品特性
- Members of the Texas Instruments Widebus™ Family
- State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Ioff and Power-Up 3-State Support Hot Insertion
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.