SN74LV123ATPWREP 供应商
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SN74LV123ATPWREP
品牌:TI 封装/批号:原厂原装/22+ -
SN74LV123ATPWREP
品牌:TI(德州仪器) 封装/批号:TSSOP-16/2022+
SN74LV123ATPWREP 属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 多频振荡器
- 系列:74LV
- 逻辑类型:单稳态
- 独立电路:2
- 施密特触发器输入:是
- 传输延迟:10.5ns
- 输出电流高,低:12mA,12mA
- 电源电压:2 V ~ 5.5 V
- 工作温度:-40°C ~ 105°C
- 安装类型:表面贴装
- 封装/外壳:16-TSSOP(0.173",4.40mm 宽)
- 供应商设备封装:16-TSSOP
- 包装:®
- 其它名称:296-22308-6
产品特性
- Controlled Baseline One Assembly/Test Site, One Fabrication Site
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of 40°C to 105°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
- Supports Mixed-Mode Voltage Operation on All Ports
- Schmitt-Trigger Circuitry on A\, B, and CLR\ Inputs for Slow Input Transition Rates
- Edge Triggered From Active-High or Active-Low Gated Logic Inputs
- Ioff Supports Partial-Power-Down Mode Operation
- Retriggerable for Very Long Output Pulses, Up To 100% Duty Cycle
- Overriding Clear Terminates Output Pulse
- Glitch-Free Power-Up Reset on Outputs
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation.This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A)\ or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.