SN74AUP1G125DPWR 供应商
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SN74AUP1G125DPWR
品牌：TI 封装/批号：原厂原装/22+ -
SN74AUP1G125DPWR
品牌：TI(德州仪器) 封装/批号：X2SON-5/2022+
SN74AUP1G125DPWR 属性参数
- 现有数量：5,590现货
- 价格：1 : ￥4.05000剪切带（CT）3,000 : ￥1.44171卷带（TR）
- 系列：74AUP
- 包装：卷带（TR）剪切带（CT）? 得捷定制卷带
- 产品状态：在售
- 逻辑类型：缓冲器，非反向
- 元件数：1
- 每个元件位数：1
- 输入类型：-
- 输出类型：三态
- 电流 - 输出高、低：4mA，4mA
- 电压 - 供电：0.8V ~ 3.6V
- 工作温度：-40°C ~ 85°C（TA）
- 安装类型：表面贴装型
- 封装/外壳：4-XFDFN 裸露焊盘
- 供应商器件封装：5-X2SON（0.8x0.8）
产品特性
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption (ICC = 0.9 µA Maximum)
- Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V)
- Low Input Capacitance (CI = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot < 10% of VCC
- Input-Disable Feature Allows Floating Input Conditions
- Ioff Supports Partial-Power-Down Mode Operation
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
- Wide Operating VCC Range of 0.8 V to 3.6 V
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.6 ns Maximum at 3.3 V
产品概述
The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state
output. The output is disabled when the output-enable (OE) input is high.
This device has the input-disable feature, which allows floating input signals.To ensure the high-impedance state during power up or power down,
OE must be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74AUP1G125DPWR 电路图
