SN74AUC240RGYR 供应商
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SN74AUC240RGYR
品牌：TI 封装/批号：原厂原装/22+
SN74AUC240RGYR 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 栅极和逆变器
- 系列：74AUC
- 逻辑类型：逆变器，缓冲器
- 电路数：2
- 输入数：4
- 特点：三态
- 电源电压：0.8 V ~ 2.7 V
- 电流 - 静态（最大值）：20µA
- 输出电流高，低：9mA，9mA
- 逻辑电平 - 低：0 V ~ 0.7 V
- 逻辑电平 - 高：1.7V
- 额定电压和最大 CL 时的最大传播延迟：1.6ns @ 2.5V，30pF
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 供应商设备封装：20-VQFN-EP（3.5x4.5）
- 封装/外壳：20-VFQFN 裸露焊盘
- 包装：®
- 其它名称：296-15436-6
产品特性
- Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub 1-V Operable
- Max tpd of 1.7 ns at 1.8 V
- Low Power Consumption, 20-µA Max ICC
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
This octal buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.This device is organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
SN74AUC240RGYR