SN74ALVCH16835DGVR 供应商
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SN74ALVCH16835DGVR
品牌：TI 封装/批号：原厂原装/22+
SN74ALVCH16835DGVR 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 - 通用总线函数
- 系列：74ALVCH
- 逻辑类型：通用总线驱动器
- 输入数：-
- 电路数：18 位
- 输出电流高，低：24mA，24mA
- 电源电压：1.65 V ~ 3.6 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：56-TFSOP（0.173"，4.40mm 宽）
- 供应商设备封装：56-TVSOP
- 包装：®
- 其它名称：296-5258-6
产品特性
- Member of the Texas Instruments Widebus™ Family
- Operates From 1.65 V to 3.6 V
- Max tpd of 3.6 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
SN74ALVCH16835DGVR