SN74ALVCH16374DLR 供应商
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SN74ALVCH16374DLR
品牌:TI 封装/批号:原厂原装/22+ -
SN74ALVCH16374DLR
品牌:TI(德州仪器) 封装/批号:SSOP-48/2022+
SN74ALVCH16374DLR 属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 触发器
- 系列:74ALVCH
- 功能:标准
- 类型:D 型总线
- 输出类型:三态非反相
- 元件数:2
- 每个元件的位元数:8
- 频率 - 时钟:150MHz
- 延迟时间 - 传输:1ns
- 触发器类型:正边沿
- 输出电流高,低:24mA,24mA
- 电源电压:1.65 V ~ 3.6 V
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:48-BSSOP(0.295",7.50mm 宽)
- 包装:®
- 其它名称:296-5226-6
产品特性
- Member of the Texas Instruments Widebus Family
- Operates From 1.65 to 3.6 V
- Max tpd of 4.2 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
产品概述
This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.The SN74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE\ can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.