IC元器件

SN74ALS666DW

参考价格:$7.9135

Texas Instruments 逻辑 - 锁销

SN74ALS666DW 供应商

SN74ALS666DW 属性参数

  • 标准包装:25
  • 类别:集成电路 (IC)
  • 家庭:逻辑 - 锁销
  • 系列:74ALS
  • 逻辑类型:D 型透明锁存器
  • 电路:8:8
  • 输出类型:三态
  • 电源电压:4.5 V ~ 5.5 V
  • 独立电路:1
  • 延迟时间 - 传输:6ns
  • 输出电流高,低:400µA, 8mA
  • 工作温度:0°C ~ 70°C
  • 安装类型:表面贴装
  • 封装/外壳:24-SOIC(0.295",7.50mm 宽)
  • 供应商设备封装:24-SOIC
  • 包装:管件
  • 其它名称:296-5081-5

产品特性

  • 3-State I/O-Type Read-Back Inputs
  • Bus-Structured Pinout
  • Choice of True or Inverting Logic SN74ALS666...True Outputs SN74ALS667...Inverted Outputs
  • SN74ALS666...True Outputs
  • SN74ALS667...Inverted Outputs
  • Preset and Clear Inputs
  • Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs

产品概述

These 8-bit D-type transparent latches are designed specifically for storing the contents of the input data bus, plus reading back the stored data onto the input data bus. In addition, they provide a 3-state buffer-type output and are easily utilized in bus-structured applications.While the latch enable (LE) is high, the Q outputs of the SN74ALS666 follow the data (D) inputs. The Q\ outputs of the SN74ALS667 provide the inverse of the data applied to its D inputs. The Q or Q\ output of both devices is in the high-impedance state if either output-enable (OE1\ or OE2\) input is at a high logic level. Read back is provided through the read-back control (OERB\) input. When OERB\ is taken low, the data present at the output of the data latches passes back onto the input data bus. When OERB\ is taken high, the output of the data latches is isolated from the D inputs. OERB\ does not affect the internal operation of the latches; however, caution should be exercised to avoid a bus conflict.The SN74ALS666 and SN74ALS667 are characterized for operation from 0°C to 70°C.

SN74ALS666DW 数据手册