SN74ALS165DR 供应商
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SN74ALS165DR
品牌:TI 封装/批号:原厂原装/22+ -
SN74ALS165DR
品牌:TI 封装/批号:/2019+
SN74ALS165DR 属性参数
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:逻辑 - 移位寄存器
- 系列:74ALS
- 逻辑类型:移位寄存器
- 输出类型:差分
- 元件数:1
- 每个元件的位元数:8
- 功能:并行或串行至串行
- 电源电压:4.5 V ~ 5.5 V
- 工作温度:0°C ~ 70°C
- 安装类型:表面贴装
- 封装/外壳:16-SOIC(0.154",3.90mm 宽)
- 供应商设备封装:16-SOIC N
- 包装:®
- 其它名称:296-29440-6
产品特性
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
产品概述
The 'ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data toward serial (QH and Q\H) outputs. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a
low level at the shift/load (SH/LD\) input. The 'ALS165 have a clock-inhibit function and
complemented serial outputs.Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and the clock inhibit (CLK INH) input is held low. The functions of
CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is low independently of the levels of the CLK, CLK INH, or serial (SER) inputs.The SN54ALS165 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS165 is characterized for operation from 0°C to 70°C.