SM320C6701GJCA12EP 供应商
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SM320C6701GJCA12EP
品牌:TI 封装/批号:原厂原装/22+ -
SM320C6701GJCA12EP
品牌:TI(德州仪器) 封装/批号:FC/CSP-352(35x35)/2022+ -
SM320C6701GJCA12EP
品牌:TI 封装/批号:FC/CSP/23+ -
SM320C6701GJCA12EP
品牌:Texas Instruments 封装/批号:/最新批号
SM320C6701GJCA12EP 属性参数
- 标准包装:21
- 类别:集成电路 (IC)
- 家庭:嵌入式 - DSP(数字式信号处理器)
- 系列:TMS320C67x
- 类型:浮点
- 接口:主机接口,McBSP
- 时钟速率:120MHz
- 非易失内存:外部
- 芯片上RAM:128kB
- 电压 - 输入/输出:3.30V
- 电压 - 核心:1.80V
- 工作温度:-40°C ~ 105°C
- 安装类型:表面贴装
- 封装/外壳:352-BBGA,FCCSPBGA
- 供应商设备封装:352-FC/CSP(35x35)
- 包装:托盘
- 其它名称:296-22215V62/03669-01XA
产品特性
- Controlled Baseline One Assembly/Test Site, One Fabrication Site
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of 40°C to 105°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Highest Performance Floating-Point Digital Signal Processor (DSP) 320C6701 8.3-ns Instruction Cycle Time 120-MHz Clock Rate Eight 32-Bit Instructions/Cycle 1 GFLOPS 320C6201 Fixed-Point DSP Pin-Compatible
- 8.3-ns Instruction Cycle Time
- 120-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1 GFLOPS
- 320C6201 Fixed-Point DSP Pin-Compatible
- VelociTI Advanced Very Long Instruction Word (VLIW) C67x CPU Core Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional
- Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point)
- Four ALUs (Floating- and Fixed-Point)
- Two ALUs (Fixed-Point)
- Two Multipliers (Floating- and Fixed-Point)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features Hardware Support for IEEE Single-Precision Instructions Hardware Support for IEEE Double-Precision Instructions Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization
- Hardware Support for IEEE Single-Precision Instructions
- Hardware Support for IEEE Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 1M-Bit On-Chip SRAM 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) 512K-Bit Dual-Access Internal Data (64K Bytes)
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes)
- 32-Bit External Memory Interface (EMIF) Glueless Interface to Synchronous Memories: SDRAM and SBSRAM Glueless Interface to Asynchronous Memories: SRAM and EPROM 52M-Byte Addressable External Memory Space
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- 52M-Byte Addressable External Memory Space
- Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
- 16-Bit Host-Port Interface (HPI) Access to Entire Memory Map
- Access to Entire Memory Map
- Two Multichannel Buffered Serial Ports (McBSPs) Direct Interface to T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible Up to 256 Channels Each AC97-Compatible Serial-Peripheral-Interface (SPI) Compatible (Motorola)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI) Compatible (Motorola)
- Two 32-Bit General-Purpose Timers
- Flexible Phase-Locked-Loop (PLL) Clock Generator
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- 352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
- 352-Pin Ball Grid Array (BGA) Mechanical Shock-Tolerant Package (Mech~Shock) Option (GJC Suffix)
- 0.18-µm/5-Level Metal Process CMOS Technology
- CMOS Technology
- 3.3-V I/Os, 1.8-V Internal (120-MHz)
- 3.3-V I/Os, 1.9-V Internal (167-MHz)
产品概述
The 320C67x DSPs are the floating-point DSP family in the TMS320C6000 DSP platform. The SM320C6701-EP and SM320C6701MECH-EP (C6701) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.