LMK04826BISQX/NOPB 供应商
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LMK04826BISQX/NOPB
品牌：TI 封装/批号：原厂原装/22+ -
LMK04826BISQX/NOPB
品牌：TI(德州仪器) 封装/批号：WQFN-64(9x9)/2022+
LMK04826BISQX/NOPB 属性参数
- 现有数量：0现货查看交期
- 价格：2,000 : ￥117.53136卷带（TR）
- 系列：PLLatinum?
- 包装：卷带（TR）
- 产品状态：在售
- 类型：抖动消除器
- PLL：是
- 输入：LVCMOS，LVDS，LVPECL
- 输出：HSDS，LCPECL，LVCMOS，LVDS，LVPECL
- 电路数：1
- 比率 - 输入:输出：3：15
- 差分 - 输入:输出：是/是
- 频率 - 最大值：2.5GHz
- 分频器/倍频器：是/无
- 电压 - 供电：3.15V ~ 3.45V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装型
- 封装/外壳：64-WFQFN 裸露焊盘
- 供应商器件封装：64-WQFN（9x9）
产品特性
- JEDEC JESD204B Support
- Ultra-Low RMS Jitter88 fs RMS Jitter (12 kHz to 20 MHz)91 fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHz
- 88 fs RMS Jitter (12 kHz to 20 MHz)
- 91 fs RMS Jitter (100 Hz to 20 MHz)
- –162.5 dBc/Hz Noise Floor at 245.76 MHz
- Up to 14 Differential Device Clocks from PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.1 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
- Up to 7 SYSREF Clocks
- Maximum Clock Output Frequency 3.1 GHz
- LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
- Up to 1 Buffered VCXO/Crystal Output from PLL1LVPECL, LVDS, 2xLVCMOS Programmable
- LVPECL, LVDS, 2xLVCMOS Programmable
- Dual Loop PLLatinum™ PLL Architecture
- PLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switch-Over ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are Lost
- Up to 3 Redundant Input ClocksAutomatic and Manual Switch-Over ModesHitless Switching and LOS
- Automatic and Manual Switch-Over Modes
- Hitless Switching and LOS
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode When Input Clocks are Lost
- PLL2 Normalized [1 Hz] PLL Noise Floor of –227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs
- Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Two Integrated Low-Noise VCOs
- 50% Duty Cycle Output Divides, 1 to 32 (even and odd)
- Precision Digital Delay, Dynamically Adjustable
- 25-ps Step Analog Delay
- Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
- Industrial Temperature Range: –40 to 85°C
- Supports 105°C PCB Temperature (Measured at Thermal Pad)
- 3.15-V to 3.45-V Operation
- Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)
产品概述
The LMK0482x family is the
industry’s highest performance clock conditioner with JEDEC JESD204B support.The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or
other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC
coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually
configured as high-performance outputs for traditional clocking systems. The high performance, combined with features such as the ability to trade off between
power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make
the LMK0482x family ideal for providing flexible
high-performance clocking trees.