DS92LV3242TVSX/NOPB 供应商
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DS92LV3242TVSX/NOPB
品牌：TI 封装/批号：原厂原装/22+ -
DS92LV3242TVSX/NOPB
品牌：TI(德州仪器) 封装/批号：TQFP-64(10x10)/2022+
DS92LV3242TVSX/NOPB 属性参数
- 制造商：National Semiconductor (TI)
- 封装：Reel
- 工厂包装数量：1000
产品特性
- Wide Operating Range Embedded Clock SER/DESUp to 32-bit Parallel LVCMOS Data 20 to 85 MHz Parallel Clock Up to 2.72 Gbps Application Data Paylod
- Up to 32-bit Parallel LVCMOS Data
- 20 to 85 MHz Parallel Clock
- Up to 2.72 Gbps Application Data Paylod
- Selectable Serial LVDS Bus WidthDual Lane Mode (20 to 50 MHz) Quad Lane Mode (40 to 85 MHz)
- Dual Lane Mode (20 to 50 MHz)
- Quad Lane Mode (40 to 85 MHz)
- Simplified Clocking ArchitectureNo Separate Serial Clock Line No reference Clock Required Receiver Locks to Random Data
- No Separate Serial Clock Line
- No reference Clock Required
- Receiver Locks to Random Data
- On-Chip Signal Conditioning for Robust Serial ConnectivityTransmit Pre-Emphasis Data Randomization DC-Balance Encoding Receive Channel Deskew Supports up to 10m CAT-5 at 2.7 Gbps
- Transmit Pre-Emphasis
- Data Randomization
- DC-Balance Encoding
- Receive Channel Deskew
- Supports up to 10m CAT-5 at 2.7 Gbps
- Integrated LVDS Terminations
- Built-in AT-SPEED BIST for End-to-End System Testing
- AC-Coupled Interconnect for Isolation and Fault Protection
- > 4KV HBM ESD Protection
- Space-Saving 64-pin TQFP Package
- Full Industrial Temperature Range : -40° to +85°C
产品概述
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock
LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or
backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes the 2 or 4 LVDS serial data
channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into
a 32-bit LVCMOS parallel data bus. On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer
Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The
Deserializer automatically locks to incoming data without an external reference clock or special
sync patterns, providing an easy “plug-and-lock” operation.By embedding the clock in the data payload and including signal conditioning functions,
the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design
effort and lower cable/connector cost for a wide variety of video, control and imaging
applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system
diagnostics.
DS92LV3242TVSX/NOPB 电路图
