CLVC2G74QDCURG4Q1 供应商
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CLVC2G74QDCURG4Q1
品牌：TI 封装/批号：原厂原装/22+
CLVC2G74QDCURG4Q1 属性参数
- 标准包装：3,000
- 类别：集成电路 (IC)
- 家庭：逻辑 - 触发器
- 系列：74LVC
- 功能：设置（预设）和复位
- 类型：D 型
- 输出类型：差分
- 元件数：1
- 每个元件的位元数：1
- 频率 - 时钟：200MHz
- 延迟时间 - 传输：1.3ns
- 触发器类型：正边沿
- 输出电流高，低：32mA，32mA
- 电源电压：1.65 V ~ 5.5 V
- 工作温度：-40°C ~ 125°C
- 安装类型：表面贴装
- 封装/外壳：8-VFSOP（0.091"，2.30mm 宽）
- 包装：带卷 (TR)
产品特性
- Qualified for Automotive Applications
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.9 ns at 3.3 V
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
产品概述
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.