CDCM1802RGTT 供应商
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CDCM1802RGTT
品牌：TI 封装/批号：原厂原装/22+ -
CDCM1802RGTT
品牌：TI 封装/批号：TSSOP/23+ -
CDCM1802RGTTG4
品牌：TI(德州仪器) 封装/批号：QFN-16(3x3)/2022+
CDCM1802RGTT 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：时钟/计时 - 时钟缓冲器，驱动器
- 系列：-
- 类型：扇出缓冲器（分配），除法器，多路复用器
- 电路数：1
- 比率 - 输入:输出：1:2
- 差分 - 输入:输出：是/是
- 输入：LVCMOS，LVPECL，LVTTL
- 输出：LVCMOS，LVPECL
- 频率 - 最大：800MHz
- 电源电压：3 V ~ 3.6 V
- 工作温度：-40°C ~ 85°C
- 安装类型：表面贴装
- 封装/外壳：16-VFQFN 裸露焊盘
- 供应商设备封装：16-QFN-EP（3x3）
- 包装：®
- 其它名称：296-17045-6
产品特性
- Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
- Programmable Output Divider for Both LVPECL and LVCMOS Outputs
- 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
- 3.3-V Power Supply (2.5-V Functional)
- Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS
- Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
- Receiver Input Threshold ±75 mV
- 16-Pin VQFN Package (3.00 mm × 3.00 mm)
产品概述
The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL
differential clock output pair, Y0 and Y0, and one single-ended LVCMOS
output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is
delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal
transitions. The CDCM1802 has two control pins, S0 and S1, to select different output mode settings.
The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable
all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be
directly connected to the unused input as a common-mode voltage reference.
CDCM1802RGTT