CD74HCT670M 供应商
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CD74HCT670M
品牌：TI 封装/批号：原厂原装/22+ -
CD74HCT670M
品牌：TI 封装/批号：TSSOP/23+
CD74HCT670M 属性参数
- 标准包装：40
- 类别：集成电路 (IC)
- 家庭：逻辑 - 移位寄存器
- 系列：74HCT
- 逻辑类型：双向寄存器
- 输出类型：标准
- 元件数：1
- 每个元件的位元数：4
- 功能：通用
- 电源电压：4.5 V ~ 5.5 V
- 工作温度：-55°C ~ 125°C
- 安装类型：表面贴装
- 封装/外壳：16-SOIC（0.154"，3.90mm 宽）
- 供应商设备封装：16-SOIC N
- 包装：管件
- 其它名称：296-9294-5
产品特性
- Simultaneous and Independent Read and Write Operations
- Expandable to 512 Words of n-Bits
- Three-State Outputs
- Organized as 4 Words x 4 Bits Wide
- Buffered Inputs
- Typical Read Time = 16ns for ’HC670 VCC = 5V, CL = 15pF, TA = 25°C
- Fanout (Over Temperature Range) Standard Outputs...10 LSTTL Loads Bus Driver Outputs...15 LSTTL Loads
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
- Wide Operating Temperature Range... –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types 2V to 6V Operation High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types 4.5V to 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min) CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
产品概述
The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE\) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE\) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE\) is low. The output is in the high impedance state when the (RE\) is high. Outputs can be tied together to increase the word capacity to 512 x 4 bits.
CD74HCT670M