CD74HC4017QPWRG4Q1 供应商
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CD74HC4017QPWRG4Q1
品牌：TI 封装/批号：原厂原装/22+
CD74HC4017QPWRG4Q1 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：逻辑 -计数器，除法器
- 系列：74HC
- 逻辑类型：计数器，十进制
- 方向：上
- 元件数：1
- 每个元件的位元数：10
- 复位：异步
- 计时：-
- 计数速率：35MHz
- 触发器类型：正边沿
- 电源电压：2 V ~ 6 V
- 工作温度：-40°C ~ 125°C
- 安装类型：表面贴装
- 封装/外壳：16-TSSOP（0.173"，4.40mm 宽）
- 供应商设备封装：16-TSSOP
- 包装：®
- 其它名称：296-31586-6
产品特性
- Qualified for Automotive Applications
- Fully Static Operation
- Buffered Inputs
- Common Reset
- Positive Edge Clocking
- Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C
- Fanout (Over Temperature Range) Standard Outputs . . . 10 LSTTL Loads Bus Driver Outputs . . . 15 LSTTL Loads
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- VCC Voltage = 2 V to 6 V
- High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V
产品概述
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.The device can drive up to ten low-power Schottky equivalent loads.