CD74AC112M96 供应商
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CD74AC112M96
品牌：TI 封装/批号：原厂原装/22+ -
CD74AC112M96
品牌：TI(德州仪器) 封装/批号：SOP-16/2022+
CD74AC112M96 属性参数
- 标准包装：2,500
- 类别：集成电路 (IC)
- 家庭：逻辑 - 触发器
- 系列：74AC
- 功能：设置（预设）和复位
- 类型：JK 型
- 输出类型：差分
- 元件数：2
- 每个元件的位元数：1
- 频率 - 时钟：100MHz
- 延迟时间 - 传输：2.6ns
- 触发器类型：负边沿
- 输出电流高，低：24mA，24mA
- 电源电压：1.5 V ~ 5.5 V
- 工作温度：-55°C ~ 125°C
- 安装类型：表面贴装
- 封装/外壳：16-SOIC（0.154"，3.90mm 宽）
- 包装：带卷 (TR)
产品特性
- AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
- Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
- Balanced Propagation Delays
- ±24-mA Output Drive Current Fanout to 15 F Devices
- Fanout to 15 F Devices
- SCR-Latchup-Resistant CMOS Process and Circuit Design
- Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
产品概述
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
CD74AC112M96