CD54HC4017F3A 供应商
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CD54HC4017F3A
品牌：TI 封装/批号：/8 -
CD54HC4017F3A
品牌：HARRIS 封装/批号：DIP/23+ -
CD54HC4017F3A
品牌：TI 封装/批号：DIP/23+ -
CD54HC4017F3A
品牌：H 封装/批号：DIP/
CD54HC4017F3A 属性参数
- 现有数量：0现货4,895Factory
- 价格：在售
- 系列：*
- 包装：管件
- 产品状态：在售
- 逻辑类型：-
- 方向：-
- 元件数：-
- 每个元件位数：-
- 复位：-
- 定时：-
- 计数速率：-
- 触发器类型：-
- 电压 - 供电：-
- 工作温度：-
- 安装类型：-
- 封装/外壳：-
- 供应商器件封装：-
产品特性
- 2-V to 6-V Operation
- Fully Static Operation
- Buffered Inputs
- Common Reset
- Positive-Edge Clocking
- Balanced Propagation Delay and Transition Times
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
- Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)
产品概述
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE\) input to cascade several stages. CE\ disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of -55°C to 125°C.