CD54ACT74F3A 供应商
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CD54ACT74F3A
品牌：Harris 封装/批号：CDIP14/21+ -
CD54ACT74F3A
品牌： 封装/批号：DIP/2019+ -
CD54ACT74F3A
品牌： 封装/批号：/23+ -
CD54ACT74F3A
品牌：TI H 封装/批号：DIP/
CD54ACT74F3A 属性参数
- 现有数量：0现货2,107Factory
- 价格：在售
- 系列：*
- 包装：管件
- 产品状态：在售
- 功能：-
- 类型：-
- 输出类型：-
- 元件数：-
- 每个元件位数：-
- 时钟频率：-
- 不同 V、最大 CL 时最大传播延迟：-
- 触发器类型：-
- 电流 - 输出高、低：-
- 电压 - 供电：-
- 电流 - 静态 (Iq)：-
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- 供应商器件封装：-
- 封装/外壳：-
产品特性
- Inputs Are TTL-Voltage Compatible
- Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
- Balanced Propagation Delays
- ±24-mA Output Drive Current Fanout to 15 F Devices
- Fanout to 15 F Devices
- SCR-Latchup-Resistant CMOS Process and Circuit Design
- Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
产品概述
The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.