CD4541BMT 属性参数
- 标准包装：1
- 类别：集成电路 (IC)
- 家庭：时钟/计时 - 可编程计时器和振荡器
- 系列：-
- 类型：可编程计时器
- 计数：65536
- 频率：100kHz
- 电源电压：3 V ~ 20 V
- 电流 - 电源：-
- 工作温度：-55°C ~ 125°C
- 封装/外壳：14-SOIC（0.154"，3.90mm 宽）
- 包装：®
- 供应商设备封装：14-SOIC
- 安装类型：表面贴装
- 其它名称：296-28573-6
产品特性
- Low Symmetrical Output Resistance, Typically 100 at VDD = 15V
- Built-In Low-Power RC Oscillator
- Oscillator Frequency Range . . . DC to 100kHz
- External Clock (Applied to Pin 3) can be Used Instead of Oscillator
- Operates as 2 N Frequency Divider or as a Single-Transition Timer
- Q/Q\ Select Provides Output Logic Level Flexibility
- AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation
- Operates With Very Slow Clock Rise and Fall Times
- Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range
- Symmetrical Output Characteristics
- 100% Tested for Quiescent Current at 20V
- 5V, 10V, and 15V Parametric Ratings
- Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
产品概述
CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input.The output from this timer is the Q or Q\ output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table).The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic "1", the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2N. With the MODE input set to logic "0" and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic "1".Timing is initialized by setting the AUTO RESET input (pin 5) to logic "0" and turning power on. If pin 5 is set to logic "1", the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, VDD should be greater than 5V.The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using:
Where f is between 1kHz and 100kHz and RS and 2RTC.