CD4502BF3A 供应商
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CD4502BF3A
品牌：TI 封装/批号：/8 -
CD4502BF3A
品牌：HAR 封装/批号：/2019+ -
CD4502BF3A
品牌：TI 封装/批号：标准封装/23+ -
CD4502BF3A
品牌：TI 封装/批号：/22+ -
CD4502BF3A
品牌：H TI 封装/批号：DIP/
CD4502BF3A 属性参数
- 现有数量：0现货2,724Factory
- 价格：在售
- 系列：4000B
- 包装：管件
- 产品状态：在售
- 逻辑类型：缓冲器，反向
- 元件数：1
- 每个元件位数：6
- 输入类型：-
- 输出类型：三态
- 电流 - 输出高、低：6.8mA，40.8mA
- 电压 - 供电：3V ~ 18V
- 工作温度：-55°C ~ 125°C（TA）
- 安装类型：通孔
- 封装/外壳：16-CDIP（0.300"，7.62mm）
- 供应商器件封装：16-CDIP
产品特性
- 2 TTL-load output drive capability
- 3-state outputs
- Common output-disable control
- Inhibit control
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Noise Margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Applications: 3-state hex inverter for interfacing IC's with data buses COS/MOS to TTL hex buffer
- 3-state hex inverter for interfacing IC's with data buses
- COS/MOS to TTL hex buffer
产品概述
CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOL standard.The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4502BF3A