CD4085BF 供应商
CD4085BF 属性参数
- 现有数量：0现货2,171Factory
- 价格：在售
- 系列：-
- 包装：管件
- 产品状态：在售
- 逻辑类型：与/或/反相门
- 电路数：2
- 输入数：8 输入（2，2，2，2）
- 施密特触发器输入：无
- 输出类型：单端
- 电流 - 输出高、低：6.8mA，6.8mA
- 电压 - 供电：3V ~ 18V
- 工作温度：-55°C ~ 125°C
- 安装类型：通孔
- 封装/外壳：14-CDIP（0.300"，7.62mm）
- 供应商器件封装：14-CDIP
产品特性
- Medium-speed operation - tPHL = 90 ns; tPLH = 125 ns (typ.) at 10 V
- Individual inhibit controls
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
产品概述
CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4085BF