ADS6445MRGCTEP 供应商
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ADS6445MRGCTEP
品牌:Texas Instruments 封装/批号:VQFN64/21+ -
ADS6445MRGCTEP
品牌:Texas Instruments 封装/批号:原厂原装/22+授权代理 -
ADS6445MRGCTEP
品牌:TI(德州仪器) 封装/批号:VQFN-64/2022+ -
ADS6445MRGCTEP
品牌:TI 封装/批号:TEJIA/21+ -
ADS6445MRGCTEP
品牌:TI 封装/批号:/23+ -
ADS6445MRGCTEP
品牌:TI 封装/批号:TSSOP/23+
ADS6445MRGCTEP 属性参数
- 产品培训模块:Data Converter Basics
- 特色产品:ADS6445 Analog-to-Digital Converter
- 标准包装:1
- 类别:集成电路 (IC)
- 家庭:数据采集 - 模数转换器
- 系列:-
- 位数:14
- 采样率(每秒):125M
- 数据接口:串行,并联
- 转换器数目:4
- 功率耗散(最大):-
- 电压电源:模拟和数字
- 工作温度:-40°C ~ 85°C
- 安装类型:表面贴装
- 封装/外壳:64-VFQFN 裸露焊盘
- 供应商设备封装:64-VQFN 裸露焊盘(9x9)
- 包装:®
- 输入数目和类型:4 个差分,单极
- 其它名称:296-23496-6
产品特性
- Maximum Sample Rate: 125 MSPS
- 14-Bit Resolution with No Missing Codes
- Simultaneous Sample and Hold
- 3.5-dB Coarse Gain and up to 6-dB Programmable Fine Gain for SFDR/SNR Trade-Off
- Serialized LVDS Outputs with Programmable Internal Termination Option
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVPP
- Internal Reference with External Reference Support
- No External Decoupling Required for References
- 3.3-V Analog and Digital Supply
- 64-pin QFN Package (9 mm × 9 mm)
- Feature Compatible Dual Channel Family
产品概述
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D
converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact
64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device
includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little
degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1
dB steps up to 6 dB. The output interface is 2-wire, where each ADC data is serialized and output over two
LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface)
and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the
traditional 1-wire interface that can be used at lower sampling frequencies.An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive
the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to
the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current
doubling modes and internal termination options. These can be used to widen eye openings and
improve signal integrity, easing capture by the receiver.The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement
or straight binary.The ADS644X has internal references, but also can support an external reference mode. The
device is specified over –55°C to 125°C operating junction temperature range.